DSD 2018

Dependability, Testing, and Fault Tolerance in Digital Systems (DTFT)

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Special Session Scope

The Euromicro Conference on Digital System Design (DSD) addresses all aspects of (embedded, pervasive and high-performance) digital and mixed HW/SW system engineering, covering the whole design trajectory from specification down to micro-architectures, digital circuits and VLSI implementations. It is a forum for researchers and engineers from academia and industry working on advanced investigations, developments and applications. It focuses on today and future challenges of advanced embedded, high-performance and cyber-physical applications; system and processor architectures for embedded and high-performance HW/SW systems; design methodology and design automation for all design levels of embedded, high-performance and cyber-physical systems; modern implementation technologies from full custom in nanometer technology nodes, through FPGAs, to MPSoC infrastructures.

Every designed system has to be tested several times during its life-time - during its design, production, and its in-field operation. The need for testing strictly depends on the actual use of the system, if the system can be repaired or not, and on the requirements for the system, e.g., if the system must be dependable, fault-tolerant, etc. The design must reflect these requirements. The special session on "Dependability, Testing, and Fault Tolerance in Digital Systems" (DTFT) addresses emerging issues, hot problems, new solution methods and their hardware and software implementations in all fields of digital and analog/mixed-signal system dependability and testing. It is especially focused on testing, dependability, and fault-tolerance of SoC based designs and modern embedded applications.

Papers on any of the following and related topics can be submitted to the special session:

• Diagnosis & testing of embedded systems, SoC and NoC testing
• Memory and CPU testing
• Analog, mixed-signal and RF, IDDQ and current testing
• Built-In Self-Test: off-line BIST and on-line BIST, test compression methods
• Testability analysis, design for testability
• Error detection and correction, on-line testing, design of checkers
• Design of dependable (robust) circuits and systems, error mitigation techniques
• Defect/fault tolerant architectures (SoCs, NoCs, embedded systems)
• FPGA based fault tolerant systems, partial/full reconfiguration based methods
• Fault injection techniques, fault simulation/emulation
• Dependability modeling, dependability analysis and validation
• Formal approaches in fault tolerant systems design
• System diagnosis
• Dependable design in practical applications

Special Session Chairs

P. Fišer (CTU in Prague, CZ)

Z. Kotásek (BUT in Brno, CZ)

Special Session Program Committee

S. Bernard, LIRMM, Montpellier (FR)

Ch. Bolchini, Politechnico di Milano (IT)

A. Bystrov, Newcastle University (UK)

L. Cassano, Politechnico di Milano (IT)

G. Di Natale, LIRMM (FR)

G. Fey, Univ. of Bremen (DE)

P. Fišer, CTU in Prague (CZ)

T. Garbolino, Silesian TU, Gliwice (PL)

M. Keim, Mentor Graphics, Wilsonville (US)

Z. Kotásek, BUT in Brno (CZ)

A. Krasniewski, WUT, Warsaw (PL)

H. Kubátová, CTU in Prague (CZ)

I. Levin, Tel Aviv University (IL)

H. Manhaeve, Q-Star Test (BE)

A. McEwan, University of Leicester (UK)

A. Miele, Politecnico di Milano (IT)

A. Orailoglu, UC, San Diego (US)

S. Racek, U. of West Bohemia (CZ)

J. Raik, Tallin U. of Technology (EE)

R. Růžička, BUT in Brno (CZ)

T. Sasao, Meiji University, Kawasaki (JP)

T. Sato, Fukuoka University (JP)

H. Shimada, Nagoya University (JP)

M. Sonza Reorda, Politecnico di Torino (IT)

A. Steininger, Vienna U. of Techn. (AT)

V. Stopjaková, STU, Bratislava (SK)

R. Ubar, TTU, Tallinn (EE)

V.S. Veravalli, Vienna U. of Techn. (AT)

H. T. Vierhaus, Brandenburg U. Tech. (DE)

Y. Zorian, Synopsys, CA (US)