Euromicro DSD/SEAA 2018

Ram K. Krishnamurthy
High performance and energy efficient SoC design challenges and opportunities for the sub-10nm technology era: From AI to IoT platforms

Abstract

This keynote presents some of the prominent barriers to designing high performance and energy-efficient microprocessors and digital systems-on-chip in the sub-10nm technology regime and outlines new paradigm shifts necessary in next-generation tera-scale multi-core microprocessors and systems-on-chip. Emerging trends in SoC design for Artificial Intelligence, Machine Learning, and IoT platforms will be discussed, and key challenges in sub-10nm design are outlined, including (i) device and on-chip interconnect technology scaling projections, (ii) performance, leakage and voltage scalability, (iii) special-purpose hardware accelerators and reconfigurable co-processors for compute-intensive signal processing algorithms, (iv) fine-grain power management with integrated voltage regulators, and (v) resilient circuit design to enable robust variation-tolerant operation. Energy-efficient arithmetic and logic circuit techniques, static/dynamic supply scaling, on-die interconnect fabric circuits, ultra-low-voltage and near-threshold logic and memory circuit techniques, and multi-supply/multi-clock domain design for switching and leakage energy reduction are described. Special purpose hardware accelerators and data-path building blocks for enabling high GOPS/Watt on specialized DSP tasks such as machine learning, encryption, graphics and video/media processing are presented. Power efficient optimization of microprocessors to span a wide operating range across high performance servers to ultra-mobile SoCs, dynamic on-the fly reconfigurability and adaptation, and circuit techniques for active/standby-mode leakage reduction with robust low-voltage operability are reviewed. Specific chip design examples and case studies supported by silicon measurements and trade-offs will be discussed. Finally, emerging industry trends in neuromorphic computing will be outlined.

Dr. Ram Kumar Krishnamurthy

Ram K. Krishnamurthy is a Senior Research Director and Senior Principal Engineer at Intel Labs, Hillsboro, Oregon. He heads the high performance and low voltage circuits research group. In this role, he leads research in high performance, energy efficient, and low voltage circuits for microprocessors and SoCs, and has made contributions to the circuit design of various generations of Intel products, including Intel® Itanium®, Pentium4®, Core®, Atom® and Xeon® line of microprocessors and SoCs. He has been at Intel Corporation since 1997.Krishnamurthy has filed over 160 patents (115 issued), and has published 150 papers and 3 book chapters on high performance energy efficient circuits. He serves as chair of the Semiconductor Research Corporation (SRC) technical advisory board for circuits, has been a guest editor of IEEE Journal of Solid-State Circuits, associate editor of IEEE transactions on VLSI systems, and on the technical program committees of ISSCC, CICC, and SOCC conferences. He served as Technical Program Chair/General Chair for the IEEE International Systems-on-Chip Conference and presently serves on the conference’s steering committee. Krishnamurthy serves as an adjunct faculty of the Electrical and Computer Engineering department at Oregon State University, where he taught advanced VLSI design. He is a board member of the industry advisory board for State University of New York. Krishnamurthy has received the IEEE International Solid State Circuits Conference distinguished technical paper award, IEEE European Solid State Circuits Conference best paper award, outstanding industry mentor award from SRC, Intel awards for most patents filed and most patents issued, Alumni recognition award from Carnegie Mellon University, distinguished alumni award from State University of New York, MIT Technology Review’s TR35 innovator award, and recognized as a top ISSCC paper contributor. He has received two Intel Achievement Awards for pioneering high performance and energy efficient microprocessor and accelerator circuit technologies on Intel products. He is a Fellow of the IEEE and distinguished lecturer of IEEE solid-state circuits society. Krishnamurthy received his BE in electrical engineering from National Institute of Technology in India (1993), MS in electrical and computer engineering from State University of New York (1994), and PhD in electrical and computer engineering from Carnegie Mellon University (1997).

Dr. Rajiv V. Joshi
Memories for Ever

Abstract

Memories are the workhorse of semiconductor industry. This is more so for Servers, main processors, Internet of Things (IoT) and System on chip applications (SOC) applications and emerging applications such cognitive computing. From neural networking perspective energy efficient logic and memories have been emphasized. This talk focuses on related to important memory circuit techniques for lowering power, improving performance and functionality in nanoscale VLSI design in the midst of variability. The usage of memories for in memory computation are brought out.

Scaling beyond 14nm technology puts burden on memories for functionality, performance, power and yield. All the key areas of memories (SRAM, Non-Volatile memories) such as reduction in active power, leakage power, short circuit power and collision power are covered. Usage of power gating, longer channel, multi-Vt design, stacking, header-footer device techniques and other innovative methods are described for memory and peripheral logic. Novel Read/write assist techniques are key for proper functionality and such circuits are described with the intention of operations at extreme low voltages.

Additional burden of technology is process, geometrical and environmental (Voltage and temperature) variation in devices. This can cause variation in power, performance and functionality of memory circuits. The talk describes how key statistical techniques and new algorithms can be effectively used to analyze and minimize variability in Volatile (SRAM, DRAM etc) and Non Volatile Memories (MRAM etc). Also the talk goes beyond the memory cell to explore the world of variability in memory peripheral, and custom logic designs. We demonstrate how statistical techniques aimed at memory designs can be effectively used to better optimize the logic itself. This increases the confidence level in the functionality and operability of the system-on-chip as a whole where model accuracies are questionable.

Artificial intelligence (AI) which is competing with Brain Intelligence (BI) has received renewed interest due to availability of higher compute power. Such demand pushes lowering of energy efficiency and throughput improvement for both edge and data centric accelerators compared to GPUs used for convolutional neural (CNN) and Deep neural (DNN) networks. The talk covers memory solutions for CNN/DNN applications at extremely low Vmin (below 0.3V).

Dr. Rajiv V. Joshi

Dr. Rajiv V. Joshi is a research staff member and key technical lead at T. J. Watson research center, IBM. He received his B.Tech I.I.T (Bombay, India), M.S (M.I.T) and Dr. Eng. Sc. (Columbia University). His novel interconnects processes and structures for aluminum, tungsten and copper technologies which are widely used globally from sub-0.5µm to 14nm. He has led successfully predictive failure analytic techniques for yield prediction and also the technology-driven SRAM at IBM Server Group. He has extensively worked on novel memory designs. He commercialized these techniques. He received 3 Outstanding Technical Achievement (OTAs), 3 highest Corporate Patent Portfolio awards for licensing contributions, holds 58 invention plateaus and has over 230 US patents and over 350 including international patents. He has authored and co-authored over 190 papers. He has given over 45 invited/keynote talks and given several Seminars. He is awarded prestigious IEEE Daniel Noble award for 2018. He received the Best Editor Award from IEEE TVLSI journal. He is recipient of 2015 BMM award. He is inducted into New Jersey Inventor Hall of Fame in Aug 2014 along with pioneer Nicola Tesla. He is a recipient of 2013 IEEE CAS Industrial Pioneer award and 2013 Mehboob Khan Award from Semiconductor Research Corporation. He is a member of IBM Academy of technology. He served as a Distinguished Lecturer for IEEE CAS and EDS society. He is Distinguished visiting professor at IIT, Roorkie. He is IEEE, ISQED and World Technology Network fellow and distinguished alumnus of IIT Bombay. He served in the Board of Governors for IEEE CAS. He serves as an Associate Editor of TVLSI. He served on committees of ISCAS 2017, ISLPED (Int. Symposium Low Power Electronic Design), IEEE VLSI design, IEEE CICC, IEEE Int. SOI conference, ISQED and Advanced Metallization Program committees. He served as a general chair for IEEE ISLPED. He is an industry liaison for universities as a part of the Semiconductor Research Corporation. Also he is in the industry liaison committee for IEEE CAS society.

Prof. Dr. Henk Corporaal, and Dr. Maurice Peemen
Accelerator Architectures for Deep Learning: Efficiency vs Flexibility?

Abstract

Deep Learning and Convolutional Neural Networks (CNNs) have revolutionized important domains like machine learning and computer vision. The huge success of deep learning accelerates research in that particular domain and thereby the complexity and diversity of state-of-the-art network models has increased significantly. This opens several challenges for CNN accelerator designers.

Computation complexity: The various layers in CNNs perform computationally expensive, and recently more irregular operations.
- Implementing convolution as General Matrix Multiplication increases the data size substantially.
- Sparse networks with even binary weight coefficients require a very different compute approach compared to the dense convolutions from the earlier networks.
Hardware efficiency: Due to the large variation of CNN model parameters across layers it is difficult to achieve a good hardware utilization.
- Wasted computation: Systolic implementations often waste a lot of computations due to padding.
- Load/store efficiency: Given an on-chip memory of limited size, the accelerator should efficiently reuse on-chip data to reduce the communication volume to external memory. Advanced loop code transformations are required to achieve acceptable efficiency levels.
- Instruction set and reconfiguration: A more flexible data path can potentially meet the diverse computational requirements of various layers. However the energy/bandwidth used for instruction fetching/decoding is overhead that should be minimized. Hardware runtime configuration can potentially give additional flexibility, but the time and resource overhead are often preventing effective use.
Designer efficiency: Writing code for efficient accelerators, especially when the networks are large and irregular, is becoming intractable. Advanced optimizing compilers and code generators are key in managing the increasing complexity.

During this keynote we will go over the state-of-the-art networks and accelerator solutions. We will present our view on compute efficiency and flexibility. We demonstrate that the well-known optimization techniques form the computing industry are key to improve efficiency. We present a holistic approach that improves efficiency by algorithmic optimizations, data reuse improvements, custom accelerators, and the less obvious but very important challenges in code generation.

Prof. Henk Corporaal

Henk Corporaal is Professor in Embedded System Architectures at the Einhoven University of Technology (TU/e) in The Netherlands. He has gained a MSc in Theoretical Physics from the University of Groningen, and a PhD in Electrical Engineering, in the area of Computer Architecture, from Delft University of Technology.

Corporaal has co-authored over 300 journal and conference papers. Furthermore he invented a new class of VLIW architectures, the Transport Triggered Architectures, which is used in several commercial products, and by many research groups.

His research is on low power multi-processor, heterogenous processing architectures, their programmability, and the predictable design of soft- and hard real-time systems. This includes research and design of embedded system architectures, accelerators, GPUs, the exploitation of all kinds of parallelism, fault-tolerance, approximate computing, architectures for machine and deep learning, and the (semi-)automated mapping of applications to these architectures. For further details see corporaal.org.

Dr. Maurice Peemen

Maurice Peemen received a MSc degree and a PhD degree in Electrical Engineering from the Eindhoven University of Technology, The Netherlands in 2011 and 2017 respectively. During his PhD his main research topics were efficiency improvements for Deep Convolutional Networks by algorithmic changes, data access optimizations, custom accelerators, and optimizing compilers. In 2015 Maurice started as Research Scientist at Thermo Fisher Scientific (formerly FEI Company) to work on high-performance microscopy workflow solutions.

Ina Schaefer
How to master the universe? - Efficiently managing variant-rich systems

Abstract

Software product line engineering has gained considerable momentum in recent years, both in industry and in academia. A software product line is a family of software products that share a common set of features. Software product lines challenge traditional analysis, test and verification techniques, in their quest of ensuring correctness and reliability of software. Simply creating and analyzing all products of a product line is usually not feasible, due to the potentially exponential number of valid feature combinations. Furthermore, software product lines require that variants are developed in a well-managed fashion which is usually not the case for existing systems. Those are often obtained by copying and modifying the cloned variants such that the commonalities and differences are not (or not sufficiently) documented. This hinders efficient maintenance and evolution of the variants for future development. In this talk, I present strategies for transforming existing legacy variants into a software product line by variability mining and show how the obtained product line structure can be exploited for efficient analysis, maintenance and evolution. The strategies will be illustrated using examples from the automotive and automation domain.

Prof. Ina Schaefer

Ina Schaefer is full professor and head of the Institute of Software Engineering and Automotive Informatics at Technische Universität Braunschweig, Germany. She received her PhD in 2008 at Technische Universität Kaiserslautern and was a Postdoc at Chalmers University, Gothenburg, Sweden. Her research interests include constructive and analytic approaches for developing correct software systems, with a particular focus on software variability and evolution, as well as re-engineering techniques for legacy software systems. The main application areas of her research are in automotive and automation.

Deepak Dhungana
Digitalization Changes Everything – are we ready to face the challenges?

Abstract

Today the virtual and the real world are seamlessly interconnected. Digitalization has changed the way we work, communicate, buy or produce things. Digitalization is a challenge – but also an opportunity for those who embrace it. In this talk, I will give an overview of the key challenges in digitalization and the Siemens approach to deal with these challenges. With its holistic approach, Siemens integrates and digitalizes the entire value chain of manufacturing companies, from design, planning, engineering to production and services. Digitalization is not a topic that is there one its own and serves its own purpose, it has to fit and meet business requirements. I will be talking about these business requirements and what it means to the scientific and commercial community to tackle these requirements in the light of digitalization offensive of the companies. Is digitalization simply a buzzword, or is it leading us anywhere soon? Are we able to take advantage of the data generated by our products and services to make better decisions? Are we ready to face the challenges?

Dr. Deepak Dhungana

Deepak Dhungana is a senior key expert and research scientist at Siemens Corporate Technology in Vienna Austria. He received his PhD from Johannes Kepler University, Linz Austria, in the area of Software Variability Management. He was a Postdoc at Lero, the irish Software Engineering Center and at Vienna University of Technology. Dhungana has co-authored over 60 journal and conference papers. Currently his research focuses on configuration technologies, particularly their application in large industrial plants. He is particularly interested in Industry 4.0 and digital transformation of production process. He is also actively involved in several large scale software engineering projects, where he keenly advocates model-driven software engineering approaches.

Pavel Dmitriev
SEAA EBEDE Session Keynote: A/B Testing for Everyone

Abstract

At Microsoft I experienced how A/B testing grew from being occasionally used by a few teams in Bing and MSN several years ago to becoming widely used by many Microsoft products including Office, Windows, xBox, Skype, Visual Studio, and others. In some products it is already a standard required part of the software release process, helping ensure software quality, understand customer value, and make better data driven decisions. In others products it is growing steadily. At Microsoft, A/B testing is winning and will soon be part of everyone's daily job. However, when I left Microsoft to join Outreach, a startup that makes sales automation software, I got exposed to a different world. Even though Outreach provided A/B testing functionality, it was rarely used and the usage was often incorrect. While the need for trustworthy decision making through A/B testing in sales was clear, it was also clear that simply giving sales teams an A/B testing system like the one we had at Microsoft will not be enough. I learned that there is a big difference between a Microsoft engineer and a sales representative, with respect to their needs for successfully using A/B testing. In this talk I will discuss the gaps. What are our experimentation platforms, tools and processes, which were built for highly trained engineers, missing to make A/B testing truly available to everyone? I will also discuss ongoing work and future research directions to fill these gaps. While required to make A/B testing a success in sales, I believe that solving these problem will also help to increase adoption and successful usage of A/B testing in the software industry.

Pavel Dmitriev

Pavel Dmitriev is a Vice President of Data Science at Outreach, where he works on enabling data driven decision making in sales through experimentation and machine learning. He was previously a Principal Data Scientist with Microsoft's Analysis and Experimentation team, where he worked on scaling experimentation in Bing, Skype, and Windows OS. His research was presented at a number of international conferences such as KDD, ICSE, WWW, CIKM, BigData, and SEAA. The exp-growth.com website he co-founded was used by over 50 companies to evaluate and grow their experimentation practices. Pavel received a Ph.D. degree in Computer Science from Cornell University in 2008, and a B.S. degree in Applied Mathematics from Moscow State University in 2002.